Computer systems have historically evolved such that succeeding generations of computer systems have had progressively greater degrees of flexibility and adaptability. For example, the first computer systems, such as ENIAC, were characterized by fixed hardware and fixed software. That is, a given configuration of hardware and software were capable of performing only a single task and the reconfiguration of either the hardware or the software for a different task was a slow and difficult process. The next major evolutionary generation of computer systems, programmable mainframes, minicomputers and microprocessors, were characterized by fixed hardware and reconfigurable software and were thereby truly programmable, being capable of storing and executing a variety of programs for different tasks.
The current generation of computer systems now includes systems utilizing field programmable gate arrays, that is, hardware comprised of dynamically reconfigurable arrays of basic functional elements, so that these systems are characterized by reconfigurable hardware as well as reconfigurable software. Systems employing field programmable gate arrays are and have been used in applications that demand the performance achieved by application specific circuits and provide the flexibility to adapt from one application to another without the installation of new, application specific hardware for each application. Field programmable gate arrays also allow systems to be upgraded or modified in accordance with rapid design cycles as a hardware reconfiguration requires only the reprogramming of the gate arrays rather than the replacement of a fixed hardware configuration.
Although current field programmable gate arrays have proven adequate and acceptable for many applications, a persistent limitation of current field programmable gate arrays is the time required to reprogram, or reconfigure, current gate arrays from one configuration to another. In the present state of the art, the reconfiguration of a field programmable gate array requires several milliseconds, and as such the reconfiguration time is much longer than the times typically required to complete processes in current computer systems. This limitation thereby prevents computer systems implemented in field programmable gate arrays from achieving run time reconfiguration, that is, the dynamic reconfiguration of system hardware during the execution of a sequence of operations so that the system hardware is optimally configured for each operation.
The prior art has attempted to deal with this limitation by the partial reconfiguration of only selected portions of the field programmable gate array elements and by the use of additional circuits, in excess of those required for system operations at any given time, with system operations switching among sets of circuits while currently unused circuits are reconfigured. In addition to increasing the complexity and cost of a system, these methods have, by there inherent nature, failed to provide a field programmable gate array based system or sub-system that can be reconfigured at a rate that exceeds the necessary persistence of a hardware function. In addition, the systems implemented by these methods have failed to provide a means whereby data may be shared between instantiations of the system hardware configurations, thereby further limiting the speed with which the hardware can be reconfigured because of the need to store and reload data at each change in the hardware configuration.
The present invention provides a solution to these and other problems of the prior art.